Array-Processed Stacked Semiconductor Packages

ABSTRACT

One embodiment of the invention is a semiconductor system ( 1400 ) of arrays ( 1401, 1402,  etc.) of packaged devices. Each array includes a sheet-like substrate ( 1411, 1412,  etc.) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound ( 1412, 1422,  etc.), which adheres to the substrate, embeds the connected components. Metal posts ( 1431, 1432,  etc.) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.

FIELD OF THE INVENTION

The present invention is related in general to the field ofsemiconductor devices and processes, and more specifically toarray-processed stacked semiconductor packages creating 3-dimensionallyinterconnected chips.

DESCRIPTION OF THE RELATED ART

The long-term trend in semiconductor technology to double the functionalcomplexity of its products every 18 months (Moore's “law”) has severalimplicit consequences. First, the higher product complexity shouldlargely be achieved by shrinking the feature sizes of the chipcomponents while holding the package dimensions constant; preferably,even the packages should shrink. Second, the increased functionalcomplexity should be paralleled by an equivalent increase in reliabilityof the product. Third, the cost per functional unit should drop witheach generation of complexity so that the cost of the product with itsdoubled functionality would increase only slightly.

As for the challenges in semiconductor packaging, the major trends areefforts to shrink the outline of a discrete package so that the packageconsumes less area and less height when it is mounted onto the circuitboard, and to reach these goals with minimum cost (both material andmanufacturing cost). Recently, another requirement was added to thislist, namely the need to design packages so that stacking of chipsand/or packages becomes an option to increase functional density andreduce device thickness. Furthermore, it is expected that a successfulstrategy for stacking chips and packages would shorten thetime-to-market of innovative products, which utilize available chips ofvarious capabilities (such as processors and memory chips) and would nothave to wait for a redesign of chips.

Recent applications especially for hand-held wireless equipments,combined with ambitious requirements for data volume and high processingspeed, place new, stringent constraints on the size and volume ofsemiconductor components used for these applications. Consequently, themarket place is renewing a push to shrink discrete semiconductor devicesboth in two and in three dimensions, and this miniaturization effortincludes packaging strategies for semiconductor devices as well aselectronic systems.

SUMMARY OF THE INVENTION

Applicants recognize the need for a fresh concept of achieving acoherent, low-cost method of assembling high lead count, yet low contourdevices. The concept includes substrates and packaging methods forstacking devices and package-on-package options as well as assemblyoptions for flip-chip and wire bond interconnections. The device can bethe base for a vertically integrated semiconductor system, which mayinclude integrated circuit chips of functional diversity and passivecomponents. The resulting system should have excellent electricalperformance, especially speed, and high product reliability. Further, itwill be a technical advantage that the fabrication method of the systemis flexible enough to be applied for different semiconductor productfamilies and a wide spectrum of design and process variations.

One embodiment of the invention is a semiconductor system of arrays ofpackaged devices. Each array includes a sheet-like substrate made ofinsulating material integral with conductive horizontal lines andvertical vias, and terminals on the surfaces. Semiconductor components,which may include more than one active or passive chip, are attached tothe substrate; the electrical connections may include flip-chip, wirebond, or combination techniques. Encapsulation compound, which adheresto the substrate, embeds the connected components. Metal posts traversethe encapsulation compound vertically, connecting the substrate viaswith pads on the encapsulation surface. The pads are covered with solderbodies used to connect to the next-level device array so that a3-dimensional system of packaged devices is formed.

In another embodiment of the invention, the system includes adistribution of the encapsulation compound so that the compoundthickness over the components is about equal to the substrate thickness.A balanced distribution of insulators is thus created, which and thus anoverall system with a high degree of robustness against thermomechanicalstress and distortion.

Another embodiment of the invention is a method for fabricating asemiconductor system, in which arrays of semiconductor packages areprocessed and then stacked to produce a 3-dimensional system of packagedcomponents. The system can be sawed into individual stacks of packageddevices. The method starts with a substrate such as a laminate tape withmetal traces patterned on the top layer. A chip is attached to the toplayer; the attachment may be performed by flip-chip technique, or bywire bonded technique. In the flip-chip version, metal posts are builtup on suitable pads on the top substrate layer; the posts need to behigh enough to allow connection to the next package layer to be stacked.In the wire bond version, wire loops are created on the top chip layerin addition to metal posts; these loops need to be high enough to allowconnection to the next package layer to be stacked. The wire bond optionallows direct chip connect to the upper stacked package.

The assembly is then overmolded so that the mold compound reaches aboutthe same thickness as the height of the posts and wire bonds and loops.The posts and bond wires are exposed using a post mold etch (wet or dry)or a polishing procedure. For the exposed wire bond version, s landingpad is deposited on the exposed wire to enable the package interconnect;the pad can also be used for routing. The molding step can be performedso that a balanced distribution of compound is achieved. The balancedstack option yields a mechanically resilient solution for the packagestacks.

The array is bonded to the next array using solder attachment on themetallization (alternatively, thermo-compression bonding may be used).The reflow of multiple stacked packages occurs at one time for the wholearray. To enhance the strength of the package, the substrate (laminatetape) can be glued or bonded to a mold cap; a mask protecting theposts/bondwires would be required for this step. Between two packagelevels, a single ground plane can be shared.

The technical advances represented by certain embodiments of theinvention will become apparent from the following description of thepreferred embodiments of the invention, when considered in conjunctionwith the accompanying drawings and the novel features set forth in theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic cross section of a portion of an arrayincluding a semiconductor component flip-assembled on a substrate andembedded in encapsulation compound, which is traversed by metal posts.

FIG. 2 depicts the schematic array portion of FIG. 1 for the case ofequal thicknesses of the substrate and the encapsulation compound on topof the component.

FIG. 3 shows a schematic top view of the array portion of FIG. 1 alongthe cut line A-A.

FIG. 4 shows a schematic top view of the array portion of FIG. 1 alongthe cut line B-B.

FIG. 5 is a schematic cross section of a stacked system of arraysincluding units assembled in the manner as illustrated in FIG. 1.

FIG. 6 is a schematic top view of the system shown in FIG. 5.

FIG. 7 shows a schematic cross section of a portion of an arrayincluding a semiconductor component attached to a substrate, wire bondedfor electrical connection, and embedded in encapsulation compound, whichis traversed by metal posts.

FIG. 8 shows a schematic top view of the array portion of FIG. 7 alongthe cut line A-A.

FIG. 9 shows a schematic top view of the array portion of FIG. 7 alongthe cut line B-B.

FIG. 10 is a schematic cross section of a stacked system of arraysincluding units assembled in the manner as illustrated in FIG. 7.

FIG. 11 illustrates a schematic cross section of a stacked system ofarrays including units with semiconductor components of different sizesor thicknesses.

FIG. 12 depicts a schematic cross section of a balanced stacked systemof arrays.

FIG. 13 shows a schematic cross section of a stacked system of arrays,which share an electrical ground plane.

FIG. 14 illustrates a schematic cross section of a stacked system ofarrays, wherein the arrays include semiconductor components of differentsizes or thicknesses and of different assembly techniques.

FIG. 15 shows a schematic cross section of a portion of an arrayincluding a stack of two semiconductor components; the first componentis flip-assembled on a substrate and the second component is wire bondedto the substrate; the stack is embedded in encapsulation compound, whichis traversed by metal posts.

FIG. 16 shows a schematic top view of the array portion of FIG. 15 alongthe cut line A-A.

FIG. 17 shows a schematic top view of the array portion of FIG. 15 alongthe cut line B-B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 illustrates a portion, generally designated 100, of an arrayshown more fully in FIG. 5. Actually it is, in FIG. 5, the first arrayof several arrays, which together form a semiconductor system. The firstarray consists of one or more assembly sites as depicted in FIG. 1; inFIG. 5, each array includes four assembly sites; arrays withconsiderably higher number of assembly sites can be manufactured. Inaddition, the sites may be arranged in x-direction as well as iny-direction; the number of sites may be different in x- and y-direction.

The assembly site depicted in FIG. 1 shows a substrate 101, which has afirst surface 101 a and a second surface 101 b. The substrate ispreferably made of a sheet-like insulating material such as polyimide-and/or epoxy-based compounds and has a thickness 101 c in the range fromabout 10 to 1000 μm. Between surfaces 101 a and 101 b are layers 102 ofconductive horizontal lines (preferably copper), and extending fromsurfaces 101 a to surface 101 b is a network of conductive vertical vias103 (preferably copper).

Substrate 101 has on the first surface 101 a two sets of terminals. Theterminals 104 of the first set are attachment sites and have ametallurgical surface composition suitable for metallic connection suchas solder bumps or gold studs. A preferred surface composition is alayer of nickel with a top layer of palladium or gold. Substrate 101further has a second set of terminals 105 on the first surface 101 a,and a third set of terminals 106 on the second surface 101 b. Preferredmetal for terminals 105 and 106 is copper; terminals 106 are suitablefor attachment of solder bodies.

In FIG. 1, a semiconductor component 110 with I/O ports 111 isflip-attached to the substrate attachment sites (first set terminals104) by means of connector bodies 112, preferably metal studs such asgold of copper bumps. Component 110 may be a discrete component, anintegrated circuit chip, or it may include a passive component such ascapacitor, an inductor, or a resistor. The thickness 110 a of thecomponent may vary from 10 to 400 μm; thicker or thinner components canbe assembled.

It should be stressed that in an array, the type of chips, the size ofthe chips, and the thickness of the chips may vary from assembly site toassembly site; consequently, one assembly site may have an integratedcircuit, the adjacent site a passive component, the next site a siliconcontrolled rectifier, etc.

Component 110 is attached onto substrate 101 by the flip-chip technique,active face down. FIG. 1 also shows an example of an electricalconnection 113 from the component 110 to substrate terminals 105 onfirst surface 101 a.

On at least portions of the second set terminals 105 on the firstsubstrate surface 101 a are metal posts 130, preferably made of copperor a copper alloy. The location of the posts matches at least portionsof the third set terminals 106 on the second substrate surface 101 b.Posts 130 are preferably about vertical to the first substrate surface101 a and have a height 130 a taller than the component thickness 110 a.The posts serve the vertical electrical connectivity and have,therefore, a diameter sufficiently wide to keep losses from inductiveand capacitive resistance minimal. The posts rest on terminals 105; onthe top end, the posts are capped by pads 131.

In FIG. 1, encapsulation compound 120 adheres to first substrate surface101 a and embeds the connected component 110. The thickness 121 of thecompound is preferably at least equal to, but more preferably greaterthan the sum of the thicknesses of component, connectors, and terminals;thickness 121 is about equal to post height 130 a. Preferably, theencapsulation material 120 is an epoxy-based molding compound, which isprocessed by the transfer molding technique.

The most preferable structure has an encapsulation compound thickness122 on top of the component 110 about equal to the thickness 201 c ofsubstrate 201. FIG. 2 illustrates an embodiment with this “balanceddistribution” of polymers (encapsulation compound and insulatingsubstrate). Experience has shown that a balanced distribution ofpolymers embedding a semiconductor component contributes to equalizecompressive stress on the component and to yield a mechanicallyresilient array structure.

Referring now to FIG. 1, attached to pads 131 are reflow metal bodies140, preferably made of tin or a tin alloy. These reflow bodies 140 havea first reflow temperature and interconnect the first array with otherarrays. After the assembly of all arrays into the semiconductor system,reflow bodies 150 may be attached to terminals 106 on the secondsubstrate surface 101 b. The reflow temperature of bodies 150 is lowerthan the reflow temperature of bodies 140.

A cross section along cut line A-A in FIG. 1 will provide a top view asillustrated in FIG. 3. The rows of pads 131 are shown in x- andy-direction. A cross section along cut line B-B in FIG. 1 will provide abottom view as illustrated in FIG. 4. The rows of posts 130 are shown inx- and y-direction. In addition, the two-dimensional array of metalstuds 112 on I/O ports 111 are indicated as round entities.

The first array of the embodiment under discussion is composed of unitsas described in FIG. 1. A complete array composed of 4 such units isillustrated in FIG. 5 in a simplified manner; the array is designated501. The array has the same type component flip-assembled in each of thefour units. In other embodiments, components for different sizes,thicknesses, and device types may be assembled as an array (anembodiment using different assembly technique is shown in FIG. 11).

A second array 502 of packaged devices is structured analogous to array501, based on units assembled as shown in FIG. 1. The array has asheet-like substrate 511 with a third surface 511 a and a fourth surface511 b, and terminals on the both surfaces. The terminals 512 on thefourth surface match the pads 131 (covered with reflow metal) of thefirst array 501.

The second array 502 is aligned and connected with the first array 501at the matching terminals 512 and 131 to form a 3-dimensional system ofpackaged devices.

A third array to an n^(th) array of packaged devices has a structureanalogous to the structure of array 502 and 501. In FIG. 5, these arraysare designated 503, 504, 505, and 506. These arrays have reflow metal ofthe same reflow temperature on all pads. After alignment, the reflowmetals of all arrays are thus connected in one process step (see below).The result is a 3-dimensional system of packaged devices. In the sideview of FIG. 5, 4 devices in the x-direction and 6 devices in they-direction are shown. Taking a top view of the pads 531 on the metalposts of top array 506 delivers FIG. 6. In the top view of FIG. 6, 4devices in the x-direction and 4 devices in the z-direction are shown.Combining the views of FIG. 5 and FIG. 6 indicates that the complete3-dimensional system includes 4×6×4=96 packaged devices.

In the embodiment of FIGS. 5 and 6, the devices have identicalcomponents; as stated earlier, other embodiments have components ofdifferent types, sizes, and thicknesses; see also FIG. 11.

The system of FIGS. 5 and 6 may be singulated into vertical stacks ofdevices. Preferably using a saw, a cut along line 540 singulates a stack541 including 1×6×4=24 packaged devices. A cut along line 550 singulatesanother stack of 1×6×4=24 packaged devices. The remaining stack 561includes 2×6×4=48 packaged devices.

Another embodiment of the invention is depicted in FIGS. 7 to 14. FIG. 7illustrates a portion, generally designated 700, of a first array shownmore fully in FIG. 10. Actually it is, in FIG. 10, the first array ofseveral arrays, which together form a semiconductor system. The firstarray consists of one or more assembly sites as depicted in FIG. 7; inFIG. 10, each array includes four assembly sites; arrays withconsiderably higher number of assembly sites can be manufactured. Inaddition, the sites may be arranged in x-direction as well as iny-direction; the number of sites may be different in x- and y-direction.

The assembly site depicted in FIG. 7 shows a substrate 701, which has afirst surface 701 a and a second surface 701 b. The substrate ispreferably made of a sheet-like insulating material such as polyimide-and/or epoxy-based compounds and has a thickness 701 c in the range fromabout 10 to 1000 μm. Between surfaces 701 a and 701 b are layers 702 ofconductive horizontal lines (preferably copper), and extending fromsurfaces 701 a to surface 701 b is a network of conductive vertical vias703 (preferably copper).

Substrate 701 may have an array of assembly sites; one of these sites isillustrated in FIG. 7. Substrate 701 has on the first surface 701 a achip attachment location 704 and two sets of terminals. The terminals705 of the first set are in proximity of component 710, preferably madeof copper and have a metallurgical surface composition suitable for wirebonding (for example gold surface layer). Substrate 701 further has asecond set of terminals 706 on the first surface 701 a, preferably madeof copper and with a metallurgical surface composition for metal postdeposition (preferably copper).

A third, a fourth, and a fifth set of terminals are on the secondsurface 701 b. Preferred metal for these terminals is copper; they aresuitable for attachment of solder bodies. The location of the third setterminals 707 match the metal posts 730; the location of the fourth setterminals 708 match the contact pads 732 on the wire span tops; and thelocation of the fifth set terminals 709 match the contact pads 733 onthe wire loop tops.

In FIG. 7, a semiconductor component 710 has an active surface 710 a, apassive surface 710 b, and a thickness 710 c. Component 710 is attachedwith its passive surface 710 b onto substrate attachment location 704.On the active surface 710 a, the component has a first set of I/O ports711, which serve as bond pads for the wire spans, and a second set ofI/O ports 712, which serve as bond pads for the wire loops. Component710 may be a discrete component, an integrated circuit chip, or it mayinclude a passive component such as capacitor, an inductor, or aresistor. The thickness 710 c of the component may vary from 10 to 400μm; thicker or thinner components can be assembled.

FIG. 7 shows two modes of electrical connection for component 710. Bondwire spans 713 connect the first set ports 711 with the respective firstset terminals 705. The wire spans reach a certain height over the activecomponent surface. Bond wire loops 714 are on each second set port 712.The tops of all loops 714 are in the same plane as the tops of the wirespans 713; the loops 714 reach the same height over the active componentsurface as the wire spans 713.

On at least portions of the second set terminals 706 on the firstsubstrate surface 701 a are metal posts 730, preferably made of copperor a copper alloy. The location of the posts matches the third setterminals 707 on the second substrate surface 701 b. Posts 730 arepreferably about vertical to the first substrate surface 701 a and havea height 730 a taller than the sum of the component thickness 710 c andthe wire loop height. The posts serve the vertical electricalconnectivity and have, therefore, a diameter sufficiently wide to keeplosses from inductive and capacitive resistance minimal. The posts reston terminals 706; on the top end, the posts are capped by pads 731.These pads match the locations of the third set terminals 707 on thesecond substrate surface 701 b.

In addition, the tops of the wire spans and the wire loops have contactpads. In FIG. 7, pads 732, contacting the wire span tops, match thelocations of the fourth set terminals 708; pads 733, in contact with thewire loop tops, match the fifth set terminals 709.

In FIG. 7, encapsulation compound 720 adheres to first substrate surface701 a and embeds the connected component 710. The thickness 721 of thecompound is about equal to post height 730 a. Preferably, theencapsulation material 720 is an epoxy-based molding compound, which isprocessed by the transfer molding technique.

The most preferable structure has an encapsulation compound thickness722 on top of the active surface 710 a of component 710 about equal tothe thickness 701 c of substrate 701. Experience has shown that a“balanced distribution” of polymers (encapsulation compound andinsulating substrate) embedding a semiconductor component contributes toequalize compressive stress on the component and to yield a mechanicallyresilient array structure.

Attached to pads 731 are reflow metal bodies 740, preferably made of tinor a tin alloy. These reflow bodies 740 have a fist reflow temperatureand interconnect the first array with other arrays. After the assemblyof all arrays into the semiconductor system, reflow bodies 750 may beattached to terminals 707, 708, and 709 on the second substrate surface701 b. The reflow temperature of bodies 750 is lower than the reflowtemperature of bodies 740.

A cross section along cut line A-A in FIG. 7 provides a top view asillustrated in FIG. 8. The rows of posts 730 are shown in x- andy-direction. A cross section along cut line B-B in FIG. 7 provides abottom view as illustrated in FIG. 9. The rows of first set terminals705 and second set terminals 706 are shown in x- and y-direction.

The first array of the embodiment under discussion is composed of unitsas described in FIG. 7. A complete array composed of 4 such units isillustrated in FIG. 10 in a simplified manner; the array is designated1001. The array has the same type component wire-assembled in each ofthe four units. In other embodiments, components for different sizes,thicknesses, and device types may be assembled as an array (anembodiment is shown in FIG. 11).

A second array 1002 of packaged devices is structured analogous to array1001, based on units assembled as shown in FIG. 7. Array 1002 has asheet-like substrate 1011 with a third surface 1011 a and a fourthsurface 1011 b, and terminals on the both surfaces. The terminals 1012on the fourth surface match the pads 731, 732, and 733 (covered withreflow metal, see FIG. 7) of the first array 1001.

The second array 1002 is aligned and connected with the first array 1001at the matching terminals 1012 and 731, 732, and 733 to form a3-dimensional system of packaged devices.

A third array to an n^(th) array of packaged devices has a structureanalogous to the structure of array 1002 and 1001. In FIG. 10, thesearrays are designated 1003, 1004, 1005, 1006, and 1007. These arrayshave reflow metal of the same reflow temperature on all pads. Afteralignment, the reflow metals of all arrays are thus connected in oneprocess step (see below). The result is a 3-dimensional system ofpackaged devices. In the side view of FIG. 10, 4 devices in thex-direction and 7 devices in the y-direction are shown.

In the embodiment of FIG. 10, the devices have identical components; asstated earlier, other embodiments have components of different types,sizes, and thicknesses. An example of these embodiments is illustratedin FIG. 11. Arrays 1101, 1102, 1104, 1105, and 1106 include components1110 of equal size and thickness, assembled by bond wires; the devicetype may be different, however. Arrays 1103 and 1107 include components1110, 1111, 1112 of different size and thickness, assembled by wirebonds.

The systems of FIGS. 10 and 11 may be singulated into vertical stacks ofdevices. Preferably using a saw, a cut along line 1040 in FIG. 10 andline 1140 in FIG. 11 singulates a stack of packaged devices. In FIG. 10,the stack is designated 1041; it includes 1×7×1=7 packaged devices underthe assumption that there is only 1 device in the z-direction. In FIG.11, the stack is designated 1141; it includes 1×7×1=7 packaged devicesunder the assuming that there is only one device in the z-direction. Theremaining stacks in FIG. 10 and FIG. 11 include 3×7×1=21 packageddevices each.

The schematic and simplified FIG. 12 illustrates another embodiment ofarray-processed stacked semiconductor packages, which emphasizes thebalancing of the stack for a mechanically resilient stack-up solution.In subassembly 1201, three arrays of packaged devices are assembled as asystem using the method described in FIG. 10. Similarly, in subassembly1202, three arrays of packaged of packaged devices are assembled as asystem using the process described in FIG. 10. Then, subassembly 1202 isflipped relative to subassembly 1201 and soldered onto subassembly 1201,using the matching reflow bodies 1210. As pointed out above, the reflowtemperature of bodies 1210 is lower than the reflow temperature of thereflow bodies used earlier in the assembly of the subassemblies; seedescription for FIG. 10. A cut along line 1220 singulates stack 1230.This stack exhibits carefully balanced mechanical characteristics forresiliency and stress robustness.

FIG. 13 depicts an embodiment, in which a single ground plane 1301 isshared by two or more array-assembled packages in a stack. As anexample, after singulating the stack 1310 from the assembled arraysalong cut-line 1320, the ground plane portion 1301 a serves the sevenpackaged devices of stack 1310.

FIG. 14 illustrates another embodiment, generally designated 1400, ofthe invention. In this example, the arrays 1401, 1402, 1403, and 1404(containing four units each) have been processed by wire bonding asdescribed in FIG. 7, and array 1405 has been processed by flip-chiptechnique as described in FIG. 1. Each array includes a sheet-likesubstrate (1411, 1412, etc.); the components may include one or moreactive or passive chips, or chips of different sizes. Encapsulationcompound (1412, 1422, etc.), which adheres to the substrate, embeds theconnected components. Metal posts (1431, 1432, etc.) traverse theencapsulation compound vertically. By means of the matching contactpads, all five arrays have been stacked by reflow assembly as a3-dimensional system. Cutting along line 1440, a stack 1450 may besingulated. This stack includes a system of devices using mixed assemblytechnologies, wire bonding and flip-chip assembly, and also mixedcomponent sizes.

Another embodiment of the invention involving mixed assemblytechnologies is depicted in FIGS. 15 to 17. This embodiment concerns astack of two or more chips, which are assembled by flip-chip as well aswire bonding techniques. FIG. 15 illustrates a portion, generallydesignated 1500, of an array. The assembly site depicted in FIG. 15shows a substrate 1501, which has a first surface 1501 a and a secondsurface 1501 b. The substrate is preferably made of a sheet-likeinsulating material such as polyimide- and/or epoxy-based compounds andhas a thickness 1501 c in the range from about 10 to 1000 μm. Betweensurfaces 1501 a and 1501 b are layers 1502 of conductive horizontallines (preferably copper), and extending from surfaces 1501 a to surface1501 b is a network of conductive vertical vias 1503 (preferablycopper).

Substrate 1501 may have an array of assembly sites; one of these sitesis illustrated in FIG. 15. Substrate 1501 has on the first surface 1501a three set of terminals. The terminals 1504 of the first set arecomponent attachment sites, preferably copper, and have a metallurgicalsurface composition suitable for metallic connection such as solderbumps or gold studs (preferably nickel with a top layer of palladium orgold). Terminals 1505 of the second set are in proximity of component1510, preferably made of copper and have a metallurgical surfacecomposition suitable for wire bonding (for example gold surface layer).Substrate 1501 further has a third set of terminals 1506 on the firstsurface 1501 a, preferably made of copper and with a metallurgicalsurface composition for metal post deposition (preferably copper).

A fourth, a fifth, and a sixth set of terminals are on the secondsurface 1501 b. Preferred metal for these terminals is copper; they aresuitable for attachment of solder bodies. The location of the fourth setterminals 1507 match the metal posts 1530; the location of the fifth setterminals 1508 match the contact pads 1532 on the wire span tops; andthe location of the sixth set terminals 1509 match the contact pads 1533on the wire loop tops.

In FIG. 15, a first semiconductor component 1510 has an active surfacewith I/O ports 1511, a passive surface, and a thickness 1510 c.Component 1510 is flip-attached with its active surface onto thesubstrate attachment sites (first set terminals 1504) by means ofconnector bodies 1512, preferably metal studs such as gold or copperbumps. Component 1510 may be a discrete component, an integrated circuitchip, or a passive component. Thickness 1510 c may vary from 10 to 400μm; thicker or thinner components can be assembled.

A second semiconductor component 1560 has an active surface 1560 a witha first and second set of I/O ports, a passive surface 1560 b, and athickness 1560 c. The first set of I/O ports 1561 serves as bond padsfor the wire spans, and the second set of I/O ports 1562 serves as bondpads for the wire loops. Component 1560 may be a discrete component, anintegrated circuit chip, or it may be a passive component. The thickness1560 c of the component may vary from 10 to 400 μm; thicker or thinnercomponents can be assembled.

The passive surface 1560 b of the second component 1560 is adhesivelyattached to the passive surface of the first component 1510.

FIG. 15 shows two modes of electrical connection for the components.Component 1510 is flip-attached and component 1560 is connected by wirebonds. Bond wire spans 1563 connect the first set ports 1561 with therespective first set terminals 1605. The wire spans reach a certainheight over the active component surface. Bond wire loops 1564 are oneach second set port 1562. The tops of all loops 1564 are in the sameplane as the tops of the wire spans 1563; the loops 714 reach the sameheight over the active component surface as the wire spans 1563.

On at least portions of the third set terminals 1506 on the firstsubstrate surface 1501 a are metal posts 1530, preferably made of copperor a copper alloy. The location of the posts matches the fourth setterminals 1507 on the second substrate surface 1501 b. Posts 1530 arepreferably about vertical to the first substrate surface 1501 a and havea height 1530 a taller than the sum of the component thicknesses 1510 cand 1560 c, and the wire loop height. The posts serve the verticalelectrical connectivity and have, therefore, a diameter sufficientlywide to keep losses from inductive and capacitive resistance minimal.The posts rest on terminals 1506; on the top end, the posts are cappedby pads 1531. These pads match the locations of the fourth set terminals1507 on the second substrate surface 1501 b.

In addition, the tops of the wire spans and the wire loops have contactpads. In FIG. 15, pads 1532, contacting the wire span tops, match thelocations of the fifth set terminals 1508; pads 1533, in contact withthe wire loop tops, match the sixth set terminals 1509.

In FIG. 15, encapsulation compound 1520 adheres to first substratesurface 1501 a and embeds the connected components 1510 and 1560. Thethickness 1521 of the compound is about equal to post height 1530 a.Preferably, the encapsulation material 1520 is an epoxy-based moldingcompound, which is processed by the transfer molding technique. The mostpreferable structure has an encapsulation compound thickness 1522 on topof the active surface 1560 a of component 1560 about equal to thethickness 1501 c of substrate 1501.

Attached to pads 1531 are reflow metal bodies 1540, preferably made oftin or a tin alloy. These reflow bodies 1540 have a fist reflowtemperature and interconnect a first array with other arrays. After theassembly of all arrays into the semiconductor system, reflow bodies 1550may be attached to terminals 1507, 1508, and 1509 on the secondsubstrate surface 1501 b. The reflow temperature of bodies 1550 is lowerthan the reflow temperature of bodies 1540.

A cross section along cut line A-A in FIG. 15 provides a top view asillustrated in FIG. 16. The rows of posts 1530 are shown in x- andy-direction. A cross section along cut line B-B in FIG. 15 provides abottom view as illustrated in FIG. 17. The rows of posts 1530 are shownin x- and y-direction. In addition, the two-dimensional array of metalstuds 1512 on I/O ports 1511 are indicated as round entities.

Another embodiment of the invention is a method for fabricating asemiconductor system as illustrated in FIGS. 5 and 6. The methodincludes the steps for fabricating a first array of packaged devicesexemplified in FIGS. 1 and 2, which includes the steps of:

providing a sheet-like substrate with a first and a second surface and athickness, the substrate made of insulating material integral withconductive horizontal lines between the surfaces and conductive verticalvias extending from the first to the second surface;

forming an array of assembly sites on the first surface, each siteincluding a first and a second set of terminals on the first surface,and a third set of terminals on the second surface;

providing semiconductor components with a thickness and I/O ports;

flip-attaching a component to each assembly site using metal studs forinterconnecting the component ports to the first set terminals;

forming metal posts at least on portions of the second set terminals,the posts being about vertical to the first surface and having a heighttaller than the component thickness, the post locations matching atleast portions of the terminals on the second surface;

embedding the connected components in encapsulation compound adhering tothe first substrate surface, the compound with a thickness at leastequal to the post height;

exposing the top surface of the posts;

depositing pads on each exposed post surface; and

depositing reflow metal of a certain reflow temperature on the pads.

The method then continues by fabricating a second array of packageddevices using the same steps as fabricating the first array. Thesubstrate of the second array has a third and a fourth surface; theterminals on the fourth surface match the reflow metal-covered pads ofthe first array; and the reflow metal has the same reflow temperature asfor the first array.

In the next step, a semiconductor system is assembled by aligning andcontacting the terminals on the fourth surface of the second array withthe reflow metal-covered pads of the first array; and then applyingthermal energy to reflow the reflow metals of both arrays to bond andelectrically connect the first and the second array.

In an optional process step, the assembled arrays can be sawedvertically to singulate individual stacks of packaged devices.

Another embodiment of the invention is a method for fabricating asemiconductor system as illustrated in FIGS. 10 to 14. The methodincludes the steps for fabricating a first array of packaged devicesexemplified in FIG. 7, which includes the steps of:

providing a sheet-like substrate with a first and a second surface and athickness, the substrate made of insulating material integral withconductive horizontal lines between the surfaces and conductive verticalvias extending from the first to the second surface;

forming an array of assembly sites, each site including a componentattach location, a first and a second set of terminals on the firstsurface, and a third, a fourth, and a fifth set of terminals on thesecond surface;

providing semiconductor components with a thickness, an active surfacewith a first and a second set of I/O ports, and a passive surface;

attaching the passive surface of a component to each substrateattachment location;

forming spans of bond wire to electrically connect the first set portsto the first set terminals, the top of all spans in a plane;

forming loops of bond wire on the second set ports, the top of all loopsin the same plane as the span tops;

forming metal posts on the second set terminals to match the locationsof the third set terminals, the posts being about vertical to the firstsurface and having a height to reach the plane of the wire span tops andwire loop tops;

embedding the connected components in encapsulation compound adhering tothe first substrate surface, the compound with a thickness at leastequal to the post height;

exposing the top surface of the posts, the wire loops, and the wirespans;

depositing a pad on the surface of each exposed top of posts, wirespans, and wire loops, the pads on the wire span tops matching thelocations of the fourth set terminals, the pads on the wire loop topsmatching the locations of the fifth set terminals; and

depositing reflow metal of a certain reflow temperature on the pads.

The method then continues by fabricating a second array of packageddevices using the same steps as fabricating the first array. Thesubstrate of the second array has a third and a fourth surface; theterminals on the fourth surface match the reflow-metal covered pads ofthe first array; and the reflow metal has the same reflow temperature asin the first array.

In the next step, a semiconductor system is assembled by aligning andcontacting the terminals on the fourth surface of the second array withthe reflow metal-covered pads of the first array; and then applyingthermal energy to reflow the reflow metals of both arrays to bond andelectrically connect the first and the second array.

In an optional process step, the assembled arrays can be sawedvertically to singulate individual stacks of packaged devices.

Another embodiment of the invention is a method for fabricating asemiconductor system, which includes the steps for fabricating a firstarray of packaged devices exemplified in FIG. 15:

providing a sheet-like substrate with a first and a second surface and athickness, the substrate made of insulating material integral withconductive horizontal lines between the surfaces and conductive verticalvias extending from the first to the second surface;

forming an array of assembly sites, each site including a first, asecond, and a third set of terminals on the first surface, and a fourth,a fifth, and a sixth set of terminals on the second surface;

providing first semiconductor components with a first thickness, anactive surface with I/O ports, and a passive surface;

flip-attaching a first component to each assembly site using metal studsfor interconnecting the ports to the first set terminals;

providing second semiconductor components with a second thickness, anactive surface with a first and a second set of I/O ports, and a passivesurface;

attaching the passive surface of a second component to the passivesurface of each first component;

forming spans of bond wire to electrically connect the first set portsto the second set terminals, the top of all spans in a plane;

forming loops of bond wire on the second set ports, the top of all loopsin the same plane as the span tops;

forming metal posts at least on portions of the second set terminals tomatch the locations of the fourth set terminals, the posts being aboutnormal to the first surface and having a height to reach the plane ofthe wire span tops and wire loop tops;

embedding the connected components in encapsulation compound adhering tothe first substrate surface, the compound with a thickness at leastequal to the post height;

exposing the top surface of the posts, the wire loops, and the wirespans;

depositing a pad on the surface of each exposed top of posts, wirespans, and wire loops, the pads on the wire span tops matching thelocations of the fifth set terminals, the pads on the wire loop topsmatching the locations of the sixth set terminals; and

depositing reflow metal of a certain reflow temperature on the pads.

The method then continues by fabricating a second array of packageddevices using the same steps as fabricating the first array. Thesubstrate of the second array has a third and a fourth surface; theterminals on the fourth surface match the reflow-metal covered pads ofthe first array; and the reflow metal has the same reflow temperature asfor the first array.

In the next step, a semiconductor system is assembled by aligning andcontacting the terminals on the fourth surface of the second array withthe reflow metal-covered pads of the first array; and then applyingthermal energy to reflow the reflow metals of both arrays to bond andelectrically connect the first and the second array.

In an optional process step, the assembled arrays can be sawedvertically to singulate individual stacks of packaged devices.

While this invention has been described in reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. It is therefore intended that the appended claims encompassany such modifications or embodiments.

1. A semiconductor system comprising: a first array of packaged devicesincluding: a sheet-like substrate having a first and a second surfaceand a thickness, the substrate made of insulating material integral withconductive horizontal lines and vertical vias, attachment sites on thefirst surface, and terminals on the first and the second surface;semiconductor components attached to the substrate attachment sites;electrical connections from the components to substrate terminals on thefirst surface; encapsulation compound adhering to the first substratesurface and embedding the connected components; metal posts traversingthe encapsulation compound vertically to connect terminals on the firstsubstrate surface with pads on the encapsulation surface; and solderbodies attached to the pads; a second array of packaged devices having asheet-like substrate with a third and a fourth surface, terminals on thefourth surface matching the solder-covered pads of the first array; andthe second array aligned and connected with the first array at thematching terminals and pads to form a 3-dimensional system of packageddevices.
 2. The system according to claim 1 further including adistribution of the encapsulation compound so that the thickness of thecompound over the components is about equal to the thickness of thesubstrate.
 3. The system according to claim 1 wherein the semiconductorcomponents include chips of active and passive devices, and stacks ofchips.
 4. The system according to claim 1 wherein the electricalconnections include flip-chip assembly, wire bonds, or both.
 5. Thesystem according to claim 1 wherein the assembled arrays are singulatedvertically into stacks of packaged devices.
 6. A semiconductor systemcomprising: a first array of packaged devices including: a sheet-likesubstrate having a first and a second surface and a thickness, thesubstrate made of insulating material integral with conductivehorizontal lines between the surfaces and conductive vertical viasextending from the first to the second surface; an array of assemblysites on the first surface, each site including a first and a second setof terminals on the first surface, and a third set of terminals on thesecond surface; a semiconductor component, having a thickness and I/Oports, flip-attached to each assembly site using metal studs forinterconnecting the chip ports to the first set terminals; metal postsat least on portions of the second set terminals, the posts being aboutvertical to the first surface, having a height taller than the componentthickness, and matching the locations of the third set terminals;encapsulation compound adhering to the first substrate surface andembedding the connected components so that the compound has a thicknessabout equal to the post height; a pad capping each post; and reflowmetal on the pads, the metal having a first reflow temperature; a secondarray of packaged devices having a sheet-like substrate with a third anda fourth surface, terminals on the fourth surface matching the reflowmetal covered pads of the first array; and the second array aligned andconnected with the first array at the matching terminals and pads toform a 3-dimensional system of packaged devices.
 7. The system accordingto claim 6 further including reflow metal bodies on the third setcontact pads of the first array, the bodies having a second reflowtemperature lower than the first reflow temperature.
 8. The systemaccording to claim 6 further including a thickness of the encapsulationcompound over the components about equal to the sheet thickness of thesubstrate.
 9. The system according to claim 6 wherein the assembledarrays are singulated vertically into stacks of packaged devices.
 10. Asemiconductor system comprising: a first array of packaged devicesincluding: a sheet-like substrate having a first and a second surfaceand a thickness, the substrate made of insulating material integral withconductive horizontal lines between the surfaces and conductive verticalvias extending from the first to the second surface; an array ofassembly sites on the first surface, each site including achip-attachment location, a first and a second set of terminals on thefirst surface and a third, a fourth, and a fifth set of terminals on thesecond surface; a semiconductor component, having a thickness, an activesurface with a first and second set of I/O ports, and a passive surface,attached with its passive surface to each attachment location; a bondwire span with a height between each first set port and the respectivefirst set terminal; a bond wire loop on each second set port, the loopsreaching the same height as the wire spans; metal posts on the secondset terminals, the posts being about vertical to the first surface,having a height taller than the sum of the component thickness and thewire loop height, and matching the locations of the third set terminals;encapsulation compound adhering to the first substrate surface andembedding the connected components so that the compound has a thicknessabout equal to the post height; a pad capping each post, wire span top,and wire loop top, the pads on the wire span tops matching the locationsof the fourth set terminals, the pads on the wire loop tops matching thelocations of the fifth set terminals; and reflow metal on the pads, themetal having a first reflow temperature; a second array of packageddevices having a sheet-like substrate with a third and a fourth surface,terminals on the fourth surface matching the reflow metal covered padsof the first array; and the second array aligned and connected with thefirst array at the matching terminals and pads to form a 3-dimensionalsystem of packaged devices.
 11. The system according to claim 10 furtherincluding reflow metal bodies on the third, the fourth, and the fifthset terminals of the first array, the bodies having a second reflowtemperature lower than the first reflow temperature.
 12. The systemaccording to claim 10 further including a thickness of the encapsulationcompound over the components about equal to the sheet thickness of thesubstrate.
 13. The system according to claim 10 wherein the assembledarrays are singulated vertically into stacks of packaged devices.
 14. Asemiconductor system comprising: a first array of packaged devicesincluding: a sheet-like substrate having a first and a second surfaceand a thickness, the substrate made of insulating material integral withconductive horizontal lines between the surfaces and conductive verticalvias extending from the first to the second surface; an array ofassembly sites on the first surface, each site including a first, asecond, and a third set of terminals on the first surface, and a fourth,a fifth, and a sixth set of terminals on the second surface; a firstsemiconductor component, having a first thickness, an active surfacewith I/O ports, and a passive surface, flip-attached to each assemblysite using metal studs for interconnecting the component ports to thefirst set terminals; a second component, having a second thickness, anactive surface with a first and a second set of I/O ports, and a passivesurface, attached with its passive surface to the passive surface of afirst component; a bond wire span with a height between each first setport and the respective second set terminal; a bond wire loop on eachsecond set port, the loops reaching the same height as the wire spans;metal posts at least on portions of the third set terminals, the postbeing about vertical to the first surface, having a height taller thanthe sum of the first and second component thicknesses and the wire loopheight, and matching the locations of the fourth set terminals;encapsulation compound adhering to the first substrate surface andembedding the connected components so that the compound has a thicknessabout equal to the post height; a pad capping each post, wire span top,and wire loop top, the pads on the wire span tops matching the locationsof the fifth set terminals, the pads on the wire loop tops matching thelocations of the sixth set terminals; and reflow metal on the pads, themetal having a first reflow temperature; a second array of packageddevices having a sheet-like substrate with a third and a fourth surface,terminals on the fourth surface matching the reflow metal coveredaligned with the first array, the contact pads on the first array; andthe second array aligned and connected with the first array at thematching terminals and pads to form a 3-dimensional system of packageddevices.
 15. The system according to claim 14 further including reflowmetal bodies on the fourth, the fifth, and the sixth set terminals ofthe first array, the bodies having a second reflow temperature lowerthan the first reflow temperature.
 16. The system according to claim 14further including a thickness of the encapsulation compound over thecomponents about equal to the sheet thickness of the substrate.
 17. Thesystem according to claim 14 wherein the assembled arrays are singulatedvertically into stacks of packaged devices.
 18. A method for fabricatinga semiconductor system comprising the steps of: fabricating a firstarray of packaged devices including the steps of: providing a sheet-likesubstrate having a first and a second surface and a thickness, thesubstrate made of insulating material integral with conductivehorizontal lines and vertical vias; forming attachment sites on thefirst surface, each site including terminals on the first and the secondsurface; providing semiconductor components having a thickness and I/Oports; attaching the components to the substrate attachment sites;connecting the components electrically to the substrate terminals on thefirst surface; forming metal posts at least on portions of the secondset terminals, the posts being vertical to the first surface and havinga height taller than the component thickness, the post locationsmatching at least portions of the terminals on the second surface;embedding the connected components in encapsulation compound adhering tothe first substrate surface, the compound having a thickness about equalto the post height; depositing pads on each post; and depositing reflowmetal on the pads, the metal having a reflow temperature; fabricating asecond array of packaged devices by the same steps as fabricating thefirst array, the substrate of the second array having a third and afourth surface, the terminals on the fourth surface matching thesolder-covered pads of the first array, and the reflow metal having thesame reflow temperature as for the first array; and assembling asemiconductor system including the steps of: aligning and contacting theterminals on the fourth surface of the second array with the reflowmetal-covered pads of the first array; and applying thermal energy toreflow the reflow metals of both arrays to bond and electrically connectthe first and the second array.
 19. The method according to claim 18wherein the step of embedding the components is performed so that theencapsulation compound has a thickness over the components about equalthe sheet thickness of the substrate.
 20. A method for fabricating asemiconductor system, comprising the steps of: fabricating a first arrayof packaged devices including the steps of: providing a sheet-likesubstrate having a first and a second surface and a thickness, thesubstrate made of insulating material integral with conductivehorizontal lines between the surfaces and conductive vertical viasextending from the first to the second surface; forming an array ofassembly sites on the first surface, each site including a first and asecond set of terminals on the first surface, and a third set ofterminals on the second surface; providing semiconductor componentshaving a thickness and I/O ports; flip-attaching a component to eachassembly site using metal studs for interconnecting the component portsto the first set terminals; forming metal posts at least on portions ofthe second set terminals, the posts being about normal to the firstsurface, having a height taller than the component thickness, andmatching the locations of the third set pads; embedding the connectedcomponents in encapsulation compound adhering to the first substratesurface, the compound having a thickness at least equal to the postheight; exposing the top surface of the posts; depositing a pad on eachexposed post surface; and depositing reflow metal on the pads, the metalhaving a reflow temperature; fabricating a second array of packageddevices by the same steps as fabricating the first array, the substratehaving a third and a fourth surface, terminals on the fourth surfacematching the reflow metal-covered pads of the first array, and thereflow metal having the same reflow temperature as in the first array;and assembling a semiconductor system, including the steps of: aligningand contacting the terminals on the fourth surface with the reflowmetal-covered pads of the first array; and applying thermal energy toreflow the reflow metals of both arrays to bond and electrically connectthe first and the second array.
 21. The method according to claim 20wherein the step of embedding the components is performed so that theencapsulation compound has a thickness over the components about equalto the sheet thickness of the substrate.
 22. The method according toclaim 20 further including the step of depositing reflow metal bodies onthe third set terminals of the first array, the bodies having a secondreflow temperature lower than the first reflow temperature.
 23. Themethod according to claim 20 further including the steps of fabricatinga third to an n^(th) array of packaged devices, including depositingreflow metals on all pads, further the steps of assembling an array ofstacked semiconductor packages by aligning the arrays of devicesrespectively, and applying thermal energy to reflow the reflow metalsbetween all arrays in one step so that all arrays are concurrentlyelectrically connected and a 3-dimensional system of packaged componentsis created.
 24. The method according to claim 20 further including thestep of sawing the assembled arrays vertically so that individual stacksof packaged devices are singulated.
 25. A method for fabricating asemiconductor system, comprising the steps of: fabricating a first arrayof packaged devices including the steps of: providing a sheet-likesubstrate having a first and a second surface and a thickness, thesubstrate made of insulating material integral with conductivehorizontal lines between the surfaces and conductive vertical viasextending from the first to the second surface; forming an array ofassembly sites, each site including a component attach location, a firstand a second set of terminals on the first surface, and a third, afourth, and a fifth set of terminals on the second surface; providingsemiconductor components having a thickness, an active surface with afirst and a second set of I/O ports, and a passive surface; attachingthe passive surface of a component to each substrate attachmentlocation; forming spans of bond wire to electrically connect the firstset ports to the first set terminals, the top of all spans in a plane;forming loops of bond wire on the second set ports, the top of all loopsin the same plane as the span tops; forming metal posts on the secondset terminals to match the locations of the third set terminals, theposts being about normal to the first surface and having a height toreach the plane of the wire span tops and wire loop tops; embedding theconnected components in encapsulation compound adhering to the firstsubstrate surface, the compound having a thickness at least equal to thepost height; exposing the top surface of the posts, the wire loops, andthe wire spans; depositing a pad on the surface of each exposed top ofposts, wire spans, and wire loops, the pads on the wire span topsmatching the locations of the fourth set terminals, the pads on the wireloop tops matching the locations of the fifth set terminals; anddepositing reflow metal on the pads, the metal having a reflowtemperature; fabricating a second array of packaged devices by the samesteps as fabricating the first array, the substrate having a third andfourth surface, terminals on the fourth surface matching reflow-metalcovered pads of the first array, and the reflow metal having the samereflow temperature as in the first array; and assembling a semiconductorsystem, including the steps of: aligning and contacting the terminals onthe fourth surface with the reflow metal-covered pads of the firstarray; and applying thermal energy to reflow the reflow metals of botharrays to bond and electrically connect the first and the second array.26. The method according to claim 25 wherein the step of embedding thecomponents is performed so that the encapsulation compound has athickness over the components about equal to the sheet thickness of thesubstrate.
 27. The method according to claim 25 further including thestep of depositing reflow metal bodies on the third, fourth and fifthset terminals of the first array, the bodies having a second reflowtemperature lower than the first reflow temperature.
 28. The methodaccording to claim 25 further including the steps of fabricating a thirdto an n^(th) array of packaged devices, including depositing reflowmetals on all pads, further the steps of assembling an array of stackedsemiconductor packages steps by aligning the arrays of devicesrespectively, and applying thermal energy to reflow the reflow metalsbetween all arrays in one step so that all arrays are concurrentlyelectrically connected and a 3-dimensional system of packaged componentsis created.
 29. The method according to claim 25 further including thestep of sawing the assembled arrays vertically so that individual stacksof packaged devices are singulated.
 30. A method for fabricating asemiconductor system, comprising the steps of: fabricating a first arrayof packaged devices including the steps of: providing a sheet-likesubstrate having a first and a second surface and a thickness, thesubstrate made of insulating material integral with conductivehorizontal lines between the surfaces and conductive vertical viasextending from the first to the second surface; forming an array ofassembly sites, each site including a first, a second, and a third setof terminals on the first surface, and a fourth, a fifth, and a sixthset of terminals on the second surface; providing first semiconductorcomponents having a first thickness, an active surface with I/O ports,and a passive surface; flip-attaching a first component to each assemblysite using metal studs for interconnecting the ports to the first setterminals; providing second semiconductor components having a secondthickness, an active surface with a first and a second set of I/O ports,and a passive surface; attaching the passive surface of a secondcomponent to the passive surface of each first component; forming spansof bond wire to electrically connect the first set ports to the secondset terminals, the top of all spans in a plane; forming loops of bondwire on the second set ports, the top of all loops in the same plane asthe span tops; forming metal posts at least on portions of the secondset terminals to match the locations of the fourth set terminals, theposts being about normal to the first surface and having a height toreach the plane of the wire span tops and wire loop tops; embedding theconnected components in encapsulation compound adhering to the firstsubstrate surface, the compound having a thickness at least equal to thepost height; exposing the top surface of the posts, the wire loops, andthe wire spans; depositing a pad on the surface of each exposed top ofposts, wire spans, and wire loops, the pads on the wire span topsmatching the locations of the fifth set terminals, the pads on the wireloop tops matching the locations of the sixth set terminals; anddepositing reflow metal on the pads, the metal having a reflowtemperature; fabricating a second array of packaged subsystems by thesame steps as fabricating the first array, the substrate having a thirdand fourth surface, terminals on the fourth surface matchingreflow-metal covered pads of the first array, and the reflow metalhaving the same reflow temperature as in the first array; and assemblinga semiconductor system, including the steps of: aligning and contactingthe terminals on the fourth surface with the reflow metal-covered padsof the first array; and applying thermal energy to reflow the reflowmetals of both arrays to bond and electrically connect the first and thesecond array.
 31. The method according to claim 30 wherein the step ofembedding the components is performed so that the encapsulation compoundhas a thickness over the components about equal to the sheet thicknessof the substrate.
 32. The method according to claim 30 further includingthe step of depositing reflow metal bodies on the fourth, fifth, andsixth set terminals of the first array, the bodies having a secondreflow temperature lower than the first reflow temperature.
 33. Themethod according to claim 30 further including the steps of fabricatinga third to an n^(th) array of packaged devices, including depositingreflow metals on all pads, further the steps of assembling an array ofstacked semiconductor package by aligning the arrays of devicesrespectively, and applying thermal energy to reflow the reflow metalsbetween all arrays in one step so that all arrays are concurrentlyelectrically connected and a 3-dimensional system of packaged componentsis created.
 34. The method according to claim 30 further including thestep of sawing the assembled arrays vertically so that individual stacksof packaged devices are singulated.